Silicide regions have historically been used to help form contacts in the connection of semiconductor devices to metallization layers in an integrated circuit. These silicide regions are generally formed by annealing a metal in contact with silicon to help reduce the contact resistance for the various devices formed as part of integrated circuits, such as CMOS transistors. In more advanced integrated circuits, other types of devices, such as bipolar devices may be integrated with the CMOS technology to form derivative technologies, such as BiCMOS or embedded flash technologies. In wafers that contain both CMOS and, e.g., bipolar devices, a single silicide process has generally been used to form silicide regions on each of the separate devices (e.g., a CMOS transistor, a bipolar transistor, etc.), forming silicide regions for all of the devices at the same time and utilizing a single process.
However, this single contact approach is undesirable for derivative technologies that comprise both CMOS devices and other types of devices. First, the derivative technologies generally generate a step height between, e.g., the CMOS transistor and a bipolar transistor, which could be as large as 3,000 Å. Further, these different devices may have differently sized contact widths, or even necessitate the formation of a silicide on a non-planar surface. These differences could lead to difficulties in integrating the different processes used to manufacture the different devices, and could even cause processing difficulties, such as over-etching, that would directly impact the functionality and, thereby, the yield, of the semiconductor devices. In addition, non-CMOS derivative devices may have different silicide sheet resistance requirements from standard CMOS.